1. Field of the Invention
This invention relates to a frequency locked loop, and in particular to a frequency locked loop suitable for use as a clock generator in integrated circuit form.
2. Description of the Related Art
It is known to use a frequency locked loop (FLL) to generate a clock signal at a frequency that is a multiple of the frequency of an existing (input) clock signal. For example, a high-frequency output clock clocks a counter. At edges of the existing clock signal, the accumulated count is latched and the counter is reset. Thus, the count represents the ratio of the frequency of the output clock to the frequency of the existing clock. This ratio is subtracted from an input value representing the desired ratio, and the resulting frequency error signal is fed to a filter. The filter integrates the frequency error to produce an integrated error signal, which is used to drive a numerically controlled oscillator, with the output of the numerically controlled oscillator being taken as the high-frequency output clock fed back to clock the counter. The feedback of the output clock means that, if its frequency becomes higher than the desired frequency, a negative frequency error signal is generated, causing the output frequency to be reduced. Conversely, if the frequency of the output clock becomes lower than the desired frequency, a positive frequency error signal is generated, causing the output frequency to increase. Thus the frequency of the generated clock converges to the desired frequency.
One application of such FLLs is in digital audio signal processing or reproduction circuitry, and in host devices employing such circuitry, including but not limited to, portable electronic devices, mobile phones, PDA's, netbooks, laptops, tablets, computers. For high quality audio reproduction it is important that the clock driving an output digital-to-analog converter has low jitter, especially in the audio frequency band, to avoid noise, distortion or spurious tones. The clock accompanying the input data may not be high quality, due to either a poor quality clock source or degradation along the transmission channel, and the clock for signal processing may need to be a multiple of the data transmission clock.
Also the generated clock must be closely synchronised to the incoming data: any accumulated clock slippage may result in dropped samples or gaps in the data to be processed.
Further, in some applications the clocks may be intermittent, perhaps due to the data being transmitted in bursts. Or the clock source may change as the modality of the host device is changed to service different use scenarios and to save any unnecessary power consumption. Yet any such clock transition should be undetectable in the reproduced audio.
Also preferably, for economic implementation in integrated circuit form, there should be minimal external components such as large capacitors: a predominantly digital solution is desirable.